Integrated circuits (ICs) are often subjected to electrostatic discharge (ESD) events through contact with a charged body (e.g., a human) that cause high voltages at one or more pins, pads or terminals of the IC. ESD events can damage an IC through thermal runaway and resultant junction shorting and/or dielectric breakdown causing gate junction shorting in metal oxide semiconductor (MOS) circuits when the amount of charge exceeds the capability of the electrical conduction path through the IC. ESD protection circuits or cells can be provided in an IC, such as clamp circuits to shunt ESD current between a protected pad and a reference node. The protected pad is often an I/O connection for conveying a time varying signal to the IC during normal operation. During normal operation, it is desirable to prevent false triggering of the ESD protection circuit due to the normal time varying signal applied to the I/O pad. Rate-triggered ESD protection circuits are often turned off during normal operation by active biasing or shut-off circuits including low-pass filter circuits and a shut-off transistor. After circuit power up, the low-pass filter provides a slowly rising gate signal to the shut-off circuit transistor which slowly turns on to disable or shut-off the ESD protection element. Conventional shut-off circuits occupy valuable area of an integrated circuit die, increases the component count and may need to be placed in an isolation region of an integrated circuit. In addition, the active shut-off circuitry can add a leakage path from power rails and decrease circuit reliability. Further, conventional active shut-off circuits increase the design and testing complexity and may decrease circuit reliability, and made themselves need protection against ESD events.